// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  efuse_cfg_4k_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 15:39:43 Create file
// ******************************************************************************

#ifndef __EFUSE_CFG_4K_REG_OFFSET_FIELD_H__
#define __EFUSE_CFG_4K_REG_OFFSET_FIELD_H__

#define EFUSE_CFG_4K_EFUSE_TSENSOR0_TRIM1_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR0_TRIM1_OFFSET 15
#define EFUSE_CFG_4K_EFUSE_TSENSOR0_TRIM0_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR0_TRIM0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_TSENSOR1_TRIM1_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR1_TRIM1_OFFSET 15
#define EFUSE_CFG_4K_EFUSE_TSENSOR1_TRIM0_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR1_TRIM0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_TSENSOR2_TRIM1_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR2_TRIM1_OFFSET 15
#define EFUSE_CFG_4K_EFUSE_TSENSOR2_TRIM0_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR2_TRIM0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_TSENSOR3_TRIM1_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR3_TRIM1_OFFSET 15
#define EFUSE_CFG_4K_EFUSE_TSENSOR3_TRIM0_LEN    11
#define EFUSE_CFG_4K_EFUSE_TSENSOR3_TRIM0_OFFSET 0

#define EFUSE_CFG_4K_HARD_REPAIR_DONE_EFUSE1_LEN    1
#define EFUSE_CFG_4K_HARD_REPAIR_DONE_EFUSE1_OFFSET 1
#define EFUSE_CFG_4K_HARD_REPAIR_DONE_EFUSE0_LEN    1
#define EFUSE_CFG_4K_HARD_REPAIR_DONE_EFUSE0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_IDDQ_HIGH_L_LEN    25
#define EFUSE_CFG_4K_EFUSE_IDDQ_HIGH_L_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_IDDQ_HIGH_H_LEN    25
#define EFUSE_CFG_4K_EFUSE_IDDQ_HIGH_H_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_IDDQ_COMMON_LEN    30
#define EFUSE_CFG_4K_EFUSE_IDDQ_COMMON_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_USB_PHY_CLK_SEL_LEN    1
#define EFUSE_CFG_4K_EFUSE_USB_PHY_CLK_SEL_OFFSET 4
#define EFUSE_CFG_4K_EFUSE_SLT_TEST_FLAG_LEN      1
#define EFUSE_CFG_4K_EFUSE_SLT_TEST_FLAG_OFFSET   3
#define EFUSE_CFG_4K_EFUSE_DVPP_VDEC_HALF_LEN     1
#define EFUSE_CFG_4K_EFUSE_DVPP_VDEC_HALF_OFFSET  2
#define EFUSE_CFG_4K_EFUSE_AI_FREQ_LOCK_LEN       2
#define EFUSE_CFG_4K_EFUSE_AI_FREQ_LOCK_OFFSET    0

#define EFUSE_CFG_4K_EFUSE_POWER_GRADE_LEN    8
#define EFUSE_CFG_4K_EFUSE_POWER_GRADE_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_TR5_AVS_ID_LEN    6
#define EFUSE_CFG_4K_EFUSE_TR5_AVS_ID_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_CHIP_NAME_LEN       16
#define EFUSE_CFG_4K_EFUSE_CHIP_NAME_OFFSET    12
#define EFUSE_CFG_4K_EFUSE_CHIP_VERSION_LEN    12
#define EFUSE_CFG_4K_EFUSE_CHIP_VERSION_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_A55_BOOT_EN_LEN    1
#define EFUSE_CFG_4K_SC_EFUSE_A55_BOOT_EN_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC1_AICORE0_LEN    10
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC1_AICORE0_OFFSET 13
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC0_AICORE0_LEN    10
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC0_AICORE0_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC1_AICORE1_LEN    10
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC1_AICORE1_OFFSET 13
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC0_AICORE1_LEN    10
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC0_AICORE1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC1_CPU_LEN    10
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC1_CPU_OFFSET 13
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC0_CPU_LEN    10
#define EFUSE_CFG_4K_SC_EFUSE_RINGOSC0_CPU_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_ALLSCAN_FORBID_LEN    1
#define EFUSE_CFG_4K_EFUSE_ALLSCAN_FORBID_OFFSET 20
#define EFUSE_CFG_4K_EFUSE_J2DJS_FORBID_LEN      1
#define EFUSE_CFG_4K_EFUSE_J2DJS_FORBID_OFFSET   16
#define EFUSE_CFG_4K_EFUSE_SJ2TDRE_FORBID_LEN    1
#define EFUSE_CFG_4K_EFUSE_SJ2TDRE_FORBID_OFFSET 12
#define EFUSE_CFG_4K_EFUSE_SDBG_CTRL_LEN         2
#define EFUSE_CFG_4K_EFUSE_SDBG_CTRL_OFFSET      8
#define EFUSE_CFG_4K_EFUSE_JTAG_FORBID_LEN       3
#define EFUSE_CFG_4K_EFUSE_JTAG_FORBID_OFFSET    4
#define EFUSE_CFG_4K_EFUSE_KEY_CFGED_LEN         1
#define EFUSE_CFG_4K_EFUSE_KEY_CFGED_OFFSET      0

#define EFUSE_CFG_4K_EFUSE_NS_FORBID_LEN    1
#define EFUSE_CFG_4K_EFUSE_NS_FORBID_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_JTAGAUTH_KEYID_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_JTAGAUTH_KEYID_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK0_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK0_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK1_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK2_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK2_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK3_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK3_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK4_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK4_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK5_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK5_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK6_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK6_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK7_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTAUK7_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_0_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_0_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_1_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_2_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_2_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_3_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_3_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_4_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_4_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_5_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_5_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_6_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_6_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_7_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK1_7_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_SUBKEYCATEGORY1_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_SUBKEYCATEGORY1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_0_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_0_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_1_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_2_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_2_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_3_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_3_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_4_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_4_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_5_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_5_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_6_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_6_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_7_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_ROTPK2_7_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_SUBKEYCATEGORY2_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_SUBKEYCATEGORY2_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK0_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK0_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK1_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK2_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK2_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK3_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK3_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK4_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK4_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK5_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK5_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK6_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK6_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_HUK7_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_HUK7_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_VERIFYFLAG_LEN    1
#define EFUSE_CFG_4K_SC_EFUSE_VERIFYFLAG_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_0_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_0_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_1_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_2_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_2_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_3_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_3_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_4_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_4_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_5_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_5_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_6_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_6_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_ST_LEN    1
#define EFUSE_CFG_4K_SC_EFUSE_OSNVCNT_ST_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_RVKSUBKEYIDMASK1_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_RVKSUBKEYIDMASK1_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_RVKSUBKEYIDMASK2_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_RVKSUBKEYIDMASK2_OFFSET 0

#define EFUSE_CFG_4K_SC_EFUSE_XLOADERNVCNT_LEN    32
#define EFUSE_CFG_4K_SC_EFUSE_XLOADERNVCNT_OFFSET 0

#define EFUSE_CFG_4K_SC_ATE_TEST_FIELD_LEN    32
#define EFUSE_CFG_4K_SC_ATE_TEST_FIELD_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_CFG_VERSION0_LEN    32
#define EFUSE_CFG_4K_EFUSE_CFG_VERSION0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_CFG_MAGIC_WORD_LEN    32
#define EFUSE_CFG_4K_EFUSE_CFG_MAGIC_WORD_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_DUAL_RAIL_MEMORY_LEN    3
#define EFUSE_CFG_4K_EFUSE_DUAL_RAIL_MEMORY_OFFSET 14
#define EFUSE_CFG_4K_EFUSE_PERI_AVS_MARGIN_LEN     3
#define EFUSE_CFG_4K_EFUSE_PERI_AVS_MARGIN_OFFSET  11
#define EFUSE_CFG_4K_EFUSE_A55_AVS_MARGIN_LEN      3
#define EFUSE_CFG_4K_EFUSE_A55_AVS_MARGIN_OFFSET   8
#define EFUSE_CFG_4K_EFUSE_AICORE1_MARGIN_LEN      4
#define EFUSE_CFG_4K_EFUSE_AICORE1_MARGIN_OFFSET   4
#define EFUSE_CFG_4K_EFUSE_AICORE0_MARGIN_LEN      4
#define EFUSE_CFG_4K_EFUSE_AICORE0_MARGIN_OFFSET   0

#define EFUSE_CFG_4K_EFUSE_NIDEN_LEN              1
#define EFUSE_CFG_4K_EFUSE_NIDEN_OFFSET           5
#define EFUSE_CFG_4K_EFUSE_DBGEN_LEN              1
#define EFUSE_CFG_4K_EFUSE_DBGEN_OFFSET           4
#define EFUSE_CFG_4K_EFUSE_SYS_ACCESS_LOCK_LEN    4
#define EFUSE_CFG_4K_EFUSE_SYS_ACCESS_LOCK_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CHECK_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_CHECK_OFFSET 2
#define EFUSE_CFG_4K_EFUSE_PATCH_EN_LEN       2
#define EFUSE_CFG_4K_EFUSE_PATCH_EN_OFFSET    0

#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR1_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR1_OFFSET 16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR0_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR3_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR3_OFFSET 16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR2_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR2_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR5_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR5_OFFSET 16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR4_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR4_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR7_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR7_OFFSET 16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR6_LEN    16
#define EFUSE_CFG_4K_EFUSE_PATCH_BUG_ADDR6_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE0_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE1_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE1_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE2_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE2_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE3_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE3_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE4_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE4_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE5_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE5_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE6_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE6_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_PATCH_CODE7_LEN    32
#define EFUSE_CFG_4K_EFUSE_PATCH_CODE7_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK_CFGED_LEN    1
#define EFUSE_CFG_4K_EFUSE_HUK_CFGED_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_DOUBLE_ROTPK_FLAG_LEN    1
#define EFUSE_CFG_4K_EFUSE_DOUBLE_ROTPK_FLAG_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_NS_MODE0_LEN    32
#define EFUSE_CFG_4K_EFUSE_NS_MODE0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_NS_MODE1_LEN    32
#define EFUSE_CFG_4K_EFUSE_NS_MODE1_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK0_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK0_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK1_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK1_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK2_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK2_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK3_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK3_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK4_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK4_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK5_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK5_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK6_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK6_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_HUK7_LEN    32
#define EFUSE_CFG_4K_EFUSE_HUK7_OFFSET 0

#define EFUSE_CFG_4K_EFUSE_NS_MODE_COMB_LEN    1
#define EFUSE_CFG_4K_EFUSE_NS_MODE_COMB_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID31_0_LEN    32
#define EFUSE_CFG_4K_DIE_ID31_0_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID63_32_LEN    32
#define EFUSE_CFG_4K_DIE_ID63_32_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID95_64_LEN    32
#define EFUSE_CFG_4K_DIE_ID95_64_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID127_96_LEN    32
#define EFUSE_CFG_4K_DIE_ID127_96_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID159_128_LEN    32
#define EFUSE_CFG_4K_DIE_ID159_128_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID191_160_LEN    32
#define EFUSE_CFG_4K_DIE_ID191_160_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID223_192_LEN    32
#define EFUSE_CFG_4K_DIE_ID223_192_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID255_224_LEN    32
#define EFUSE_CFG_4K_DIE_ID255_224_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID287_256_LEN    32
#define EFUSE_CFG_4K_DIE_ID287_256_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID319_288_LEN    32
#define EFUSE_CFG_4K_DIE_ID319_288_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID351_320_LEN    32
#define EFUSE_CFG_4K_DIE_ID351_320_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID383_352_LEN    32
#define EFUSE_CFG_4K_DIE_ID383_352_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID415_384_LEN    32
#define EFUSE_CFG_4K_DIE_ID415_384_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID447_416_LEN    32
#define EFUSE_CFG_4K_DIE_ID447_416_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID479_448_LEN    32
#define EFUSE_CFG_4K_DIE_ID479_448_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID511_480_LEN    32
#define EFUSE_CFG_4K_DIE_ID511_480_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID543_512_LEN    32
#define EFUSE_CFG_4K_DIE_ID543_512_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID575_544_LEN    32
#define EFUSE_CFG_4K_DIE_ID575_544_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID607_576_LEN    32
#define EFUSE_CFG_4K_DIE_ID607_576_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID639_608_LEN    32
#define EFUSE_CFG_4K_DIE_ID639_608_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID671_640_LEN    32
#define EFUSE_CFG_4K_DIE_ID671_640_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID703_672_LEN    32
#define EFUSE_CFG_4K_DIE_ID703_672_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID735_704_LEN    32
#define EFUSE_CFG_4K_DIE_ID735_704_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID767_736_LEN    32
#define EFUSE_CFG_4K_DIE_ID767_736_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID799_768_LEN    32
#define EFUSE_CFG_4K_DIE_ID799_768_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID831_800_LEN    32
#define EFUSE_CFG_4K_DIE_ID831_800_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID863_832_LEN    32
#define EFUSE_CFG_4K_DIE_ID863_832_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID895_864_LEN    32
#define EFUSE_CFG_4K_DIE_ID895_864_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID927_896_LEN    32
#define EFUSE_CFG_4K_DIE_ID927_896_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID959_928_LEN    32
#define EFUSE_CFG_4K_DIE_ID959_928_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID991_960_LEN    32
#define EFUSE_CFG_4K_DIE_ID991_960_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1023_992_LEN    32
#define EFUSE_CFG_4K_DIE_ID1023_992_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1055_1024_LEN    32
#define EFUSE_CFG_4K_DIE_ID1055_1024_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1087_1056_LEN    32
#define EFUSE_CFG_4K_DIE_ID1087_1056_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1119_1088_LEN    32
#define EFUSE_CFG_4K_DIE_ID1119_1088_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1151_1120_LEN    32
#define EFUSE_CFG_4K_DIE_ID1151_1120_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1183_1152_LEN    32
#define EFUSE_CFG_4K_DIE_ID1183_1152_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1215_1184_LEN    32
#define EFUSE_CFG_4K_DIE_ID1215_1184_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1247_1216_LEN    32
#define EFUSE_CFG_4K_DIE_ID1247_1216_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1279_1248_LEN    32
#define EFUSE_CFG_4K_DIE_ID1279_1248_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1311_1280_LEN    32
#define EFUSE_CFG_4K_DIE_ID1311_1280_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1343_1312_LEN    32
#define EFUSE_CFG_4K_DIE_ID1343_1312_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1375_1344_LEN    32
#define EFUSE_CFG_4K_DIE_ID1375_1344_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1407_1376_LEN    32
#define EFUSE_CFG_4K_DIE_ID1407_1376_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1439_1408_LEN    32
#define EFUSE_CFG_4K_DIE_ID1439_1408_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1471_1440_LEN    32
#define EFUSE_CFG_4K_DIE_ID1471_1440_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1503_1472_LEN    32
#define EFUSE_CFG_4K_DIE_ID1503_1472_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1535_1504_LEN    32
#define EFUSE_CFG_4K_DIE_ID1535_1504_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1567_1536_LEN    32
#define EFUSE_CFG_4K_DIE_ID1567_1536_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1599_1568_LEN    32
#define EFUSE_CFG_4K_DIE_ID1599_1568_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1631_1600_LEN    32
#define EFUSE_CFG_4K_DIE_ID1631_1600_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1663_1632_LEN    32
#define EFUSE_CFG_4K_DIE_ID1663_1632_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1695_1664_LEN    32
#define EFUSE_CFG_4K_DIE_ID1695_1664_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1727_1696_LEN    32
#define EFUSE_CFG_4K_DIE_ID1727_1696_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1759_1728_LEN    32
#define EFUSE_CFG_4K_DIE_ID1759_1728_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1791_1760_LEN    32
#define EFUSE_CFG_4K_DIE_ID1791_1760_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1823_1792_LEN    32
#define EFUSE_CFG_4K_DIE_ID1823_1792_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1855_1824_LEN    32
#define EFUSE_CFG_4K_DIE_ID1855_1824_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1887_1856_LEN    32
#define EFUSE_CFG_4K_DIE_ID1887_1856_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1919_1888_LEN    32
#define EFUSE_CFG_4K_DIE_ID1919_1888_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID1983_1952_LEN    32
#define EFUSE_CFG_4K_DIE_ID1983_1952_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID2015_1984_LEN    32
#define EFUSE_CFG_4K_DIE_ID2015_1984_OFFSET 0

#define EFUSE_CFG_4K_DIE_ID2047_2016_LEN    32
#define EFUSE_CFG_4K_DIE_ID2047_2016_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID31_0_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID31_0_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID63_32_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID63_32_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID95_64_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID95_64_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID127_96_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID127_96_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID159_128_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID159_128_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID191_160_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID191_160_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID223_192_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID223_192_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID255_224_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID255_224_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID287_256_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID287_256_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID319_288_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID319_288_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID351_320_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID351_320_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID383_352_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID383_352_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID415_384_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID415_384_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID447_416_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID447_416_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID479_448_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID479_448_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID511_480_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID511_480_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID543_512_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID543_512_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID575_544_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID575_544_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID607_576_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID607_576_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID639_608_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID639_608_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID671_640_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID671_640_OFFSET 0

#define EFUSE_CFG_4K_DIE_S_ID703_672_LEN    32
#define EFUSE_CFG_4K_DIE_S_ID703_672_OFFSET 0

#define EFUSE_CFG_4K_SYSCTRL_LOCK_LEN    32
#define EFUSE_CFG_4K_SYSCTRL_LOCK_OFFSET 0

#define EFUSE_CFG_4K_SYSCTRL_UNLOCK_LEN    32
#define EFUSE_CFG_4K_SYSCTRL_UNLOCK_OFFSET 0

#define EFUSE_CFG_4K_ECO_RSV1_LEN    32
#define EFUSE_CFG_4K_ECO_RSV1_OFFSET 0

#define EFUSE_CFG_4K_ECO_RSV2_LEN    32
#define EFUSE_CFG_4K_ECO_RSV2_OFFSET 0

#define EFUSE_CFG_4K_ECO_RSV3_LEN    32
#define EFUSE_CFG_4K_ECO_RSV3_OFFSET 0

#define EFUSE_CFG_4K_ECO_RSV4_LEN    32
#define EFUSE_CFG_4K_ECO_RSV4_OFFSET 0

#define EFUSE_CFG_4K_ECO_RSV5_LEN    32
#define EFUSE_CFG_4K_ECO_RSV5_OFFSET 0

#define EFUSE_CFG_4K_FPGA_VERI_NUM_LEN    32
#define EFUSE_CFG_4K_FPGA_VERI_NUM_OFFSET 0

#endif // __EFUSE_CFG_4K_REG_OFFSET_FIELD_H__
